Flash memory stores data in arrays of memory elements, or cells, formed from floating-gate transistors. NAND flash memory devices return previously stored data by reading a series of bits from individual cells in an array. Within the array, an analog charge level can be stored in each cell. A sense amplifier connected to the array senses and converts the charge level from an analog format to a digital format. When used to represent binary numbers, the digital representation of the analog charge level stored in the cell can be recognized as a 0 or 1 value.
Charge leakage, or transfer, can alter the analog charge level stored in each cell. This changes the voltage level that is sensed and converted to the digital format. As a result, the digital value that is read can be different from the value that was originally stored, or programmed, in the cell. This problem is often referred to as a bit flip. Some bit flips can be detected and corrected by error correction code (ECC). The number of bit flips that can be detected and corrected is dependent on the amount of ECC processing resources available within a particular system.
As cell geometries get smaller with improved semiconductor fabrication techniques, the smaller geometries can cause an increase in bit-line capacitance. Bit-line capacitance refers to the interference caused by a signal on one bit-line of the array with another signal on another bit-line of the array. To deal with potential problems resulting from increased bit-line capacitance, sense amplifiers may be more sensitive to distinguish between relatively small voltage differentials, which establish the thresholds between digital values used to represent the analog charge levels. Otherwise, a bit flip may occur. The sensitivity of a sense amplifier can typically be improved by increasing the amount of time that the sense amplifier is allowed to access, or read, the analog charge level from a corresponding cell. This time that the sense amplifier is sensing and converting the analog charge level, along with pre- and post-processing activities, is often referred to as the read time (tREAD) of the array. Thus, typical tREAD times in NAND flash memory devices are increasing to compensate for smaller geometries and increased bit-line capacitance. This increase in tREAD times results in longer overall times to access data from a NAND flash memory device.
Throughout the description, similar reference numbers may be used to identify similar elements.